Design Engineer To Verification Engineer: Clocking Block in SystemVerilog

The clocking block used to separate the timing and synchronization specifications of signal like- input sampling time, output driving time from details the structural, functional, and procedural elements of a testbench. Thus, the timing for sampling and driving clocking block signals is implicit and relative to the clocking-block’s clock. This enables a set of key operations to be written very clearly, without explicitly using clocks or specifying timing. These operations are:

— Synchronous events

— Input sampling

— Synchronous drives

Clocking blocks can only be declared inside a module, interface or program. The clocking construct is both the declaration and the instance of that declaration. The signal directions in the clocking block within the testbench are with respect to the testbench, also that widths are not declared in the clocking block, just the directions.

Example CB syntax: (clk1 period is 10ns)

// Clocking outputs are DUT inputs and

// Clocking inputs are DUT outputs
clocking cb_name @(posedge clk1); // clocking event is posedge of clk1

// clocking skews
default input #1 output #4ns; // 1ns input skew and 4ns output skew

// if time unit did not mentioned (as in output skew) current time unit

// from the time scale will be taken (input skew).

output negedge rst;

// signal identifiers name of the signal should be same as in DUT

// unless it’s a hierarchical name (cross module reference)
output dut_sig1;

output dut_sig2;

output dut_sig3 = sig3_hierarchical;

.

.
input dut_sig1;

input dut_sig2;

input #3 dut_sig3;

.

.
endclocking

The clocking_event (posedge clk1) designates a particular event to act as the clock for the clocking block. Typically, this expression is either the posedge or negedge of a clocking signal. All input or inout signals specified in the clocking block are sampled when the corresponding clock event occurs. All output or inout signals in the clocking block are driven when the corresponding clock event occurs. Bidirectional signals (inout) are sampled as well as driven.

The clocking_skew determines how many time units away from the clock event a signal is to be sampled or driven. Input skews are implicitly negative, that is, they always refer to a time before the clock, whereas output skews always refer to a time after the clock. When the clocking event specifies a simple

edge, instead of a number, the skew can be specified as the specific edge of the signal. A single skew can be specified for the entire block by using a default clocking item (as shown in the example). So in our example sig1 and sig2 samples 1ns after the posedge of clk1 where as sig3 samples after 3ns.

* The clocking event of a clocking block is available directly by using the clocking block name

clocking dram @(posedge phi1);

inout data;

output negedge #1 address;

endclocking

For the above clocking block, @( dram ); is equivalent to @(posedge phi1)

* Cycle delay: ##

Used to delay execution by a specified number of clocking events, or clock cycles

## 5; // wait 5 cycles (clocking events) using the default clocking

## (j + 1); // wait j+1 cycles (clocking events) using the default clocking

Finally, clocking block provides explicit synchronization through event control operator @. i.e. a process can wait for a particular signal change .

Wait for the next change of signal ack_1 of clocking block ram_bus

@(ram_bus.ack_l);